One of the concerns regarding TSVs’ application with memory, in particular, is that DRAM performs poorly at junction temperatures above 85ºC. Keeping the memory contents refreshed at higher temperatures requires more current, which itself leads to more heating of the die. There are limits to what can be standardised, and many of the issues around assembly, test and heat dissipation from the 3D-IC stack will need to be addressed by each customer.
Assembly continues to be a major concern in the industry. Many of the processing steps involved in creation of TSVs can create mechanical, thermal or electrical stresses on the die being processed for TSV. These stresses may change the properties of the device.
Manufacturing test is another issue. For example, finding a method to probe TSVs with a diameter of 10 mm each and on a 50mm grid could prove problematic. Allowing the probe head to contact more than 2000 TSVs at a time without damage is another example. As the industry works to resolve these issues, we will surely see logic devices with TSV-connected DRAM in the next few years.
Leading applications for 2.5D/3D ICs
“One of the initial applications for 2.5D is large FPGAs. For example, Xilinx’ stacked silicon interposer solution, which was announced in 2010 and began shipping in December 2011. 2.5D is also being used for integration of memory with CPUs in complex, multi-die SoCs. The motivation is higher communication bandwidth with memory, overall lower system power consumption and smaller footprint. Semico has indicated that large pitch interposers also have opportunities in applications such as MEMs and RF,” shares Sawicki.
“Semico also reports that initial full 3D products using TSVs are appearing in camera and memory products. Toshiba is making a TSV camera module for cell phones that was introduced before CES in January 2012, and Samsung released engineering samples in August 2011 for a DRAM module using TSVs. For the most part, 3D-IC technology is still evolving and expected to enter high-volume production in the next three to four years. For example, Samsung and Micron have joined hands to create a consortium for what they call the hybrid memory cube. This consortium is designed to create standards that will allow development and adoption of 3D technology for stacked die memory modules.”
One key question is, “Does the learning curve involve re-adjustment of roles and responsibilities in the manufacturing flow?” According to Sawicki, there are some interesting interactions between IC design and packaging groups and their roles, depending on who gets the assignment to design the overall 2.5D/3D assembly. If an IC design group gets the assignment, it uses IC design tools; if packaging group gets the assignment, it tries to use packaging tools/methodologies, driving some interesting new product requirement discussions.
“There is still much discussion on whether the foundry or OSAT will own wafer thinning and stacking and test. One new constraint is that whoever owns the stacking process will also have to own test as he will need to ensure KGD as well as support any partial stack testing,” he adds.
Future trends
Talking about the future 3D-IC technology trends, their timeline and impact on EDA, Ahuja shares: “Despite the lingering challenges and unanswered questions, the semiconductor industry is starting to work on the wealth of functionality and performance that 2.5D/3D IC promises. According to Yole Development, the shipment volume of 3D-IC wafers will touch 10 million units in 2012. Designers and engineers can now build and design energy-efficient and better-performance systems using heterogeneous technologies such as MEMS, CMOS and silicon photonics through the enablement of 2.5D and 3D-IC technology.
“Memories and sensors markets are anticipated to provide the largest market owing to the growing demand for enhanced design methodologies that can be used in a wide variety of applications. Among the application sectors, consumer electronics segment largely adds to the overall evolution of the market. In the forthcoming days, it is likely that newer applications such as hybrid memory, graphics processor unit, low-density parity check decoder and cell broadband engine will rise to serve as prospective markets for 3D ICs and TSV.”
The author was executive editor at EFY till recently
