From magnetic disks to solid storage we have developed many efficient storage products. Today the people are opting for faster and large capacity storage devices. Is that true?
Let’s take a look at some of these devices with Mr. Vivian Singh, CEO, Strontium Technology India Pvt Ltd.
How has the development of storage chips come about in recent years?
We saw a jump of few gigabyte storage to recent 200GB within the 11mm×15mm×1mm form factor of microSD card. We are now at the mature stage of 14nanometer (nm) semiconductor device lithographic fabrication node.
The most-dense process for creating silicon flash memory cells to store data on planar NAND is between 10 nanometre (nm) and 19nm in size. To give some idea of how small that is, a nanometre is one-billionth of a meter – a human hair is 3,000 times thicker than NAND flash made with 25nm process technology. There are 25 million nanometres in an inch.
It would not be a surprise to see the capacity flip and performance scooted in the near future.
What are some of the recent trends and advances affecting memory design?
With this current scenario, we foresee requirement for low capacity legacy cards still persists. While uptrend seeking for huge capacity card demand is there but its unamusing as the hardware (host) which can support SDXC card is limited or undergoing the compatibility tuning stage.
With flash technology advancement from the beginning of SLC, MLC to TLC and now 3D NAND, greater capacity flash storage would be a norm in the near future to come.
With Google announcing Android 6 – Marshmallow supporting “adoptable storage”, we foresee an extreme capacity external storage that would be dominating the products when the host hardware adopts the standard and stabilized version of Marshmallow.
Challenges in adopting the latest advances in designing equipment.
There is always a challenge to bring the laboratories (theoretical) experiment to practical and actual mass production. This would affect the supply chain right from the wafer FAB to all the way till the host devices.
Wafer yield would be another challenge due to the high density and while fine tuning is the common standard for the industries across, requires a run-in period to enhance the processes.
Challenges in R&D for storage chips.
As the name implies – Research (theory) & Development (fact), it is always a tough deal to find the right match and blend the two together to get the best fit for both the worlds. It applies same for storage chips as well, which need to meet the physical settings and fulfil the performance/behaviour with various hosts and adapt to new requirement and standards.
3-D NAND technology, advantages and limitations.
Restrained by the convention 2D planar, 3D NAND is the only way to break through the NAND flash architecture. Three-dimensional NAND takes today’s flash, which is built on a horizontal plane, and turns it sideways.
Similar as microscopic memory skyscrapers, it stacks them side-by-side to create a vastly denser chip with twice the write performance and 10 times the reliability of today’s 2D, or planar, NAND. 3D NAND technology achieves high density by stacking layers of cells on top of each other in a vertical NAND string structure, rather than shrinking the cells at the planar level.
This way, higher bit density is achieved for a smaller footprint, and the lithography patterning limitation is eliminated.
Some benefits and limitations with such technology.
We can count the advantages as;
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- Consume much lesser power – It reduces cell-to-cell interference and thus the number of programming steps has been vastly reduced and along with other improvements, power consumption will be substantially lower.
- Higher Reliability – With the vertical 3D cell architecture that is being formed in 3D NAND, the interference between bits the lines is almost zero. Thus, substantially reduce the capacitive coupling between neighbouring cells.
- Higher Performance – Since 3D NAND technology is less sensitive to cell-to-cell interference, it can write data significantly faster, resulting in better performance.
And the limitation as;
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- As per Fatalism of Moore’s law, we are not sure how many stack layer can it goes, as 3D NAND cells are formed vertically.
Adoption of technology, user compatibility, and ease of integration for designers.
The journey of no return has already begun, as the market is heading towards growth and strong “focus” to adopt 3D NAND. It would be a new learning curve for the whole supply chain but the process should be brief. But we certainly foresee some compatibility issue especially for the low-end and “cost effective” host hardware. Integration will be mild since it has to abide by the standard form-factor laid by the association.
