But more than any other factor, ensuring the availability of a solution that provides a significant improvement in on-wafer performance with low risk was essential to get customers to adopt the new single-wafer standard on a significant enough scale.
Q. You did your Ph.D. on In-situ Integrated Rapid Thermal Processing of Advanced Materials and Devices. How has the adoption of RTP technology in dynamic random access memory (DRAM) integrated circuits helped today’s electronics industry?
A. What the adoption of RTP enabled is basically scaling DRAMs below the 0.6 micron technology node. Today the industry is scaling to the 25nm node. Once proven in DRAM manufacturing, RTP was adopted in the manufacture of other devices such as logic, non-volatile memory, analog and MEMS. Today, single RTP is a fundamental enabling technology in the fabrication of the most advanced semiconductor devices.
Q. Could you give us an insight on the emerging technologies in the semiconductor industry?
A. The next 5 years are expected to see more technology inflections and shifts than the past 15 years. A major inflection starting to play out now is the fundamental shift to 3D device architectures – such as finFET in the logic space, and 3D NAND in flash memory. Realizing these complex structures requires more process steps, to selectively deposit or removal material with highly repeatable precision in a volume manufacturing environment.
On a longer-term horizon, we can expect to see the 450mm inflection, during which the wafer-size standard moves from 300mm (12”) diameter to 450mm (18”). We’re currently in the R&D stage of developing tools for the 450mm wafer standard.
Q. Silicon is almost always used in designing and manufacturing ICs. Is there any research being done on alternate material?
A. As mentioned, tools have evolved to be able to selectively deposit or remove a wide variety of materials previously unknown to semiconductor processing with very high levels of precision.
In terms of the substrate itself, there is quite a lot of fundamental research ongoing in academia. A good example is the usage of Graphene as a basic substrate material. There are certain process steps in packaging schemes (such as interposers) where glass can be considered as an alternative to silicon.
Nevertheless, the well understood electrical and physical properties of silicon handling, and the economics of processing, make us believe that silicon is to remain the mainstay substrate material of choice for quite some years to come.
Q. Congratulations on your recent career achievement on becoming an IEEE Fellow. Would you like to share your thoughts on that?
A. It is certainly a prestigious honor and I am very humbled to receive it. I consider it as one of the highlights of my career, and I’m pleased to have been able to make a meaningful contribution to the industry. It’s gratifying to know that my work on the development and implementation of single-wafer RTP technology has led to key improvements in device performance and manufacturing cycle time.
