EDA is providing the enabling technologies and infrastructure that help foster innovative SoC designs. The innovation in EDA itself has also led to the combination of more processes and new IP to create next-generation designs.
Dilin Anand and Sneha Ambastha of EFY spoke to Dr. Ajoy Bose, Chairman, President and CEO, Atrenta Inc. and Sushil Gupta, Vice President and Managing Director, Atrenta India about the EDA industry and the importance of RTL signoff. Read further to find some interesting facts about the usage of SpyGlass in the EDA design flow.
Q. What are the three most important challenges that are tackled using EDA tools?
A. There is a large ecosystem of IP that spans everything, created by large companies like ARM as well as other smaller firms creating IP for various applications such as cameras, video processing and various types of wireless applications such as Bluetooth, wi-fi and the like. Integrating these functions is one thing that EDA enables for system-on-chip, or SoC design.
Companies now design SoCs based on 28nm and below semiconductor processes. The thing that drives the SoC is the technology node and these technology nodes bring benefits of higher density, higher performance and lower power.
The third driving force for SoCs is the all-important economics of the chip. The cost of developing an SoC has become very expensive. There are creative ways to design a less expensive chip, however. In this complex industry, depending on who you are and where you are in the chip eco-system, you may have different priorities. People that are creating hand-held devices are more concerned about power, while those who are creating wired applications are more concerned about performance. On the other hand, anything linked to the consumer industry has a time to market pressure because the consumer market is very cyclic. EDA plays an important role here in providing enabling technologies and infrastructure to help put the IPs together and create an SoC that meets the time to market, power, performance and cost requirements of the application.
Q. What is the most preferred technique to offset chip complexity, which increases with every functionality added?
A. There are a number of techniques and probably the most common technique is to utilize a higher level of abstraction. In a way, an SoC is like Lego blocks (a child’s game) where the blocks are assembled together. In today’s world, when there are hundreds of millions of transistors used in a single chip, analyzing and optimizing the design at the transistor or at gate level is very difficult. There is just too much data. If we consider the IP blocks of the design things become easier. Using this level of abstraction – IP blocks at the register transfer level (RTL), it is much easier to process the data and make changes. It can be an order of magnitude faster in many cases. These IP blocks can be thought of as the Lego blocks that must be assembled efficiently.
Q. Are there any innovative/out-of-the-box enhancements making their way here?
A. Two items come to mind. First, the reuse of very complex IP blocks, called subsystems. Thanks to well-defined interface protocols, large-scale blocks can now be interfaced easily, bringing the abstraction level even higher. The second is more efficient use of design hierarchy. Using the design hierarchy correctly lets you “divide and conquer” complexity. For example, you need only check the internals of a block once and then use it many times in the chip, each time only checking the interface and not the internals over and over again.
Q. Could you elaborate on the importance of RTL signoff process?
A. If you look into the trends in SoC design, one of the key points is to select IP blocks that have high quality, are robust and provide you with the functionality you need. Atrenta’s SpyGlass analyzer plays an important role in this early IP block selection process. We have a set of functions that we offer to our customers that help them to analyze the overall quality of the IP block. Analyzing the block means predicting the cost, power consumption and performance of the block and how it will function in the SoC.
So the first analysis takes place at each block and then a similar analysis is performed at the full SoC level when all the blocks are put together. We are able to predict the cost, performance and power consumption of the design before it is actually implemented in detail. We call this process RTL signoff. Then comes the role of the major EDA tools that are provided by the big players like Cadence, Synopsys and Mentor for detailed implementation. From there the SoC is taken to the fabrication level.
Q. What is the key differentiator here compared to conventional tools?
A. The key differentiator is that they work at a much higher level of abstraction, called RTL. At the early level of design we can predict things like power, performance and cost before the expensive and time-consuming process of detailed implementation begins. Designers can make decisions early and optimize the design so that the rest of the process has a smaller number of iterations and is more cost-effective.
