RISC-V (pronounced “risk-five”) is an open instruction set architecture (ISA) based on the reduced instruction set computing (RISC). What sets it apart from other ISAs is that the RISC-V ISA can be freely used for any purpose, permitting anyone to design, manufacture and sell RISC-V chips and software. While not the first open architecture ISA, it is significant because it is designed to be useful in a wide range of devices.
Yunsup Lee, Co-Founder & Chief Technology Officer at SiFive, and Krste Asanovic, Co-Founder & Chief Architect at SiFive speak to us in an interview with Dilin Anand from EFY.
Co-Founder & Chief Technology Officer at SiFive
Co-Founder & Chief Architect at SiFive
What sparked the creation of RISC-V?
We wanted a simple clean ISA that was efficient to implement and easy to extend to add specialised accelerators. We also wanted to be able to share with others. The tipping point was realising we were wasting time adapting commercial ISAs to our needs, and we could never share the results once we were done.
What were some of the initial guidelines your founding team decided to set in stone, to ensure that the RISC-V economy/ecosystem scaled as it did?
First, we mandated that the ISA spec and compatibility suites would always be free. Second, we froze the specification when we released version 2.0 in 2014 to provide stability. Third, we created an independent non-profit Foundation to provide a stable long-lived home for the ISA.
DID YOU KNOW THE INDIAN ANGLE?
The Indian Institute of Technology Madras is developing six RISC-V open-source CPU designs for six distinct uses, from a small 32-bit CPU for the Internet of Things (IoT) to large, 64-bit CPUs designed for warehouse-scale computers such as server farms based on RapidIO and Hybrid Memory Cube technologies.
From among the various open source licenses available, what was the line of reasoning used to select BSD for RISC-V?
We wanted to encourage and facilitate widespread use in the industry. We knew a non-permissive license would have impeded the spread of the ISA and our implementations.
What are the focus areas for RISV-V Foundation members over the next 12 months?
We are focused on improving RISC-V in the embedded space, adding faster interrupts, packed-SIMD (Single instruction, multiple data) extensions, and providing a new embedded application binary interface (ABI), as well as adding vector instructions for AI (artificial intelligence) and standardising various parts of the RISC-V security architecture.
What were the initial bottle-necks faced as you set out to define the importance of an open ISA over pre-existing open source hardware?
Initially, many were under the impression that we were providing a single free implementation rather than a broadly usable spec. There are now many open-source cores available all compatible with a single spec.
What’s the plan to drive the community around RISC-V to grow and thrive across the world?
The Foundation now has 100+ companies as members and is expanding its charter to help accommodate the demand which is far greater than we ever anticipated three years ago when we started the Foundation. The Foundation will be launching many more events around the world, coordinating with governments to help with educational outreach, and developing research programs, and vocational training materials for practitioners. We will also continue to extend the ISA with new features and support for the rapid growth of the software ecosystem.
