The intellectual property (IP) can be in many different shapes and forms: software, hardware, on-chip, on-board, soft IP, hard IP, design IP, verification IP, etc. Assuming that we are talking of silicon IP, the designs have only become more complex with a lot of different interfaces being integrated onto the same piece of silicon.
According to Giles Peckham, EMEA marketing director, today’s advanced 28nm design processes enable FPGA companies to put up to one million logic cells onto a single piece of silicon.
“Creating designs of hundreds of thousands of logic cells, especially when performance requirements are high, requires the use of IP from the FPGA vendor, third parties and typically reuse of previously designed modules. Electronic system level (ESL) synthesis tools can help maintain high levels of productivity but these are used today to create additional high-level IP blocks,” he says.
Anil Gupta, managing director, Applied Micro Circuits India, says, “The advanced technology nodes allow greater integration and this further creates an opportunity to put more varied interfaces on the same chip. Given the enormity of globally distributed teams working on these chips and the complexities involved in simply designing and implementing the core portions, there is an acute awareness and push to identify reliable suppliers of various IP blocks, especially those which are considered standard fare or those which require specialised skills like analogue or mixed-signal. These include the typical memory interfaces like DDRx, peripheral interfaces like USB, SDIO/eMMC, analogue IP like the data converters, etc.”
For early designs at a particular technology node, the challenge remains that the IP is often developed and verified at the same time as the chip development. Often the manufacturing process technology is also evolving at the same time, complicating this even further. This adds significant risk to the schedules, as the IP may not be production-ready by the time the chip needs to tape-out. IPs for advanced nodes often take a couple of rounds of silicon to end up bug-free.
Irrespective of the risks involved, design teams today have little choice but to go to IP developers to get whatever IP they can. That is the only way to meet the tight schedules and time-lines (thus improving design productivity), according to Gupta.
Jaswinder Ahuja, corporate vice president and managing director, Cadence Design Systems in India, adds, “Over the last few years, the rapid growth in the consumption of electronic gadgets such as wireless handsets, tablets, gaming devices, 3G-/WiMax-enabled netbooks, set-top boxes and smart cards has increased design complexity. At the same time, semiconductor companies are under constant time-to-market pressures to bring out newer designs more quickly and at lower costs.”
Increasingly, IP is becoming an option for companies to address the issues of complexity, time-to-market and profitability. As per the data from ChipEstimate.com, Cadence’s chip planning solutions business unit, the IP portion has grown from around 40 per cent in 2004 to 70-80 per cent today in ASICs and ASSPs. This is based on well over 100,000 chip estimations, so the data is quite extensive.
This leads us to the question of expense management and how it’s driving the growth of third-party IP vendors.
Expense management
Peckham notes that the demand for third-party IP has been created more by the need to achieve productivity levels that enable FPGA designers to quickly get their products into emerging markets rather than the need to reduce design costs.
He adds, “For third-party IP vendors to thrive, they also need to deliver their IP in a package of representations that conform to industry standards and are compatible with multiple FPGA product families.”
Ahuja says, “While the use of commercial and in-house IP can reduce the overall cost of the design, integration is a challenge and there has been an increase in the cost to integrate various IP blocks into a complex SoC architecture. These costs continue to rise with each new generation of SoC largely driven by the dramatic increase in the number of IP blocks infused into the architecture.”
Another aspect to cost and profitability is the amount of effort made by the silicon designers to create the advanced SoC architectures expected by end-users for each new generation of silicon.
The IP ecosystem needs to change so that SoC design can adopt a system-level-driven approach to resolve issues like those mentioned above. The IP must be designed from a system-level point of view from the very beginning in order to make it easier for the silicon architect to adopt and use in his design. At the same time, the IP must allow for ease of integration into the design.
