Richard also notes, “while many microcontroller solutions have embedded flash, the memory density in many cases is not large enough to store the entire system firmware, especially as application feature sets increase and user interfaces become more interactive and sophisticated. Therefore systems will still incorporate an external flash solution for direct code execution or for code shadowing.”
Write/erase speed on flash memories
Writing to flash memories is a slow process. Harry Kitt, R&D technical associate, Spacelabs Healthcare, shares, “when the system needs to store substantial data, the real-time element is suspended for the system’s first purpose. when you are considering the dump-truck-sized flash chip, keep in mind that the only way to fill it is wit a teaspoon.”
Explaining how the write/erase operation works, Rosenboim says, “Typically, the write speed of flash memories is of the order of a few microseconds per byte, but a write operation will only change bits from ‘1’ to ‘0’. So to write arbitrary data, an entire ‘block’ must be erased first, which will turn all bits to ‘1’.”
It is a major limitation of flash memories that these can read or program a byte or a word at a time, but can be erased only in blocks. So the rewrite and erase operations are not in random-access fashion. An erase operation takes 0.1 to 5 seconds, depending on the specific technology, and typically erases 64 to 128 kB at a time.
Some vendors offer a type of flash memory that helps alleviate the drawback of spending hundreds or thousands of milliseconds to erase large blocks of memory by allowing the system to erase very small pages of memory. Explaining further, Richard says, “You can erase as little as 256 bytes of memory at a time, and the erase typically takes less than 15 milliseconds. This kind of erase granularity provides the added benefit of not forcing the system to erase more memory than is actually needed for a particular operation, which allows the system to optimise the memory array usage and the system performance.”
Flash components primarily come with either of three interface types: Parallel, byte-serial and bit-serial. Rosenboim says, “Since the NOR flash has traditionally been used to replace the EPROM and ‘eXecute In Place’ the code, it has a parallel address/data interface that is ‘memory mapped’ onto any type of processor by directly interfacing its local bus signals.”
Today, the price of the NOR flash has come down to a point where its package is the most significant component of the cost. To reduce the cost further, a reduction in the number of pins on the package resulted in introduction of ‘bit-serial’ interface components like serial peripheral interface (SPI) based flash. These parts require a special module in the microprocessor to initialise its DRAM controller and copy the entire boot code section into the DRAM for execution.
“Typically, NAND flash components come with a byte-serial interface, where a command byte and a few address bytes are followed by a whole ‘page’ worth of data bytes on the same 8-bit data interface. That is, the bytes are serially transmitted between the flash device and the microprocessor,” shares Rosenboim.
“The more recent NOR flash based devices—those with multi-level cells—have become much slower to erase than their predecessors. four seconds to erase a 128k block is truly slow by any measure, but it appears these are made necessary by the changes in technology that lead to lower cost per bit and higher densities,” he adds.
On the positive side, these newer NOR parts have an improved erase-suspend ability. So with a bit more complexity of the software layer, one can mitigate this problem by suspending the erase process to let other activities execute while performing the erase operations in the background effectively. This is much less of a problem than all operations being blocked for the duration of a ‘block erase’ operation.
