Q. What are the biggest challenges the semiconductor industry is facing today?
A. Semiconductor is a union of multiple industries. There is a sector of the industry, which is at 14nm. There is a large sector of the industry which is happy at 65nm and I don’t think they are going to move in the near future. The biggest challenge, according to me, how to constantly keep on innovating in this space. Bigger still is how you capture value out of that innovation. This is an industry that is innovating so fast, you are left behind if you do not. Yet, the price at which you keep selling your product keeps decreasing year on year.
Q. How is the industry is looking at process nodes today?
A. One of the primary drivers for looking at newer nodes is cost per transistor. While this saw a decrease till 28nm, we see the costs slowly increasing, as you venture beyond. The primary reason for this is that, while the cost of the manufacturing process and the wafer itself has gone down, there is a rise in the cost of design and that of the manufacturing set-up. What this means is that there is a need for advanced lithography techniques and others, resulting in increasing costs as you move to lower nodes.
Q. Why are people interested in lower nodes?
A. People are, however, still interested in lower nodes. With lower nodes come lower power, which is creating interest in the field of hand-held devices. But, a shift to lower nodes also causes problems with return-on-investment (ROI). Statistics say that a transition could cost about 200 million dollars for a single chip. So, the volume of production influences the decision on transition. There is also another side to this. A typical SoC has memory, logic and few analogue blocks. Memory doesn’t scale easily and you cannot shrink it the way you do logic. The same goes for analogue. Thus, the incremental yield in terms of investment is limited. Fabs need to now support a large portfolio, with volume production happening at 130, 65, 28 and 14nm.
Q. What capabilities do transitioning to lower nodes introduce from a usage or application perspective?
A. The transition to lower nodes is seen only in mobile and computing industries. These are spaces where heavy-duty computing is necessary, making it needed to pack more transistors into a piece of silicon. Also, power is sensitive.
Q. What are the design challenges that crop up when you move to lower nodes?
A. The layout offers a lot of difficulties, simply from a capacitance point of view. With the half pitch being so small, the parasitic capacitance between tracks shoots up, resulting in design rule clean-up and other such issues. Managing leakage current has been a constant challenge since we hit 40-odd nm, and it becomes more acute as you move progressively lower. There is a science that says that at 3nm, the silicon effectively stops behaving like a semiconductor. 3nm would be about six atoms of silica. Therefore leakage current tends to become much more of a problem.
Q. Other than moving into lower nodes, what other changes do you see creating innovations in the semiconductor industry?
A. There is a huge interest towards functional safety lately. Especially with the auto industry booming, people are beginning to ask “How can you certify to me that your chip will not fail?” Traditional verification works around functionality. Safety-related testing demands a creating a perfectly-working chip, not just at the time of going in for manufacturing, but till the lifetime of the car. During its life-time, the car might go through a volley of harsh conditions like extreme temperature changes, electromagnetic interference, or other such harsh conditions, leading to the silicon fabric undergoing physical wear and tear. The chances that a transistor burns itself out, about three or four years into the field, is quite high. This kind of verification offers a whole new set of interesting technical challenges.
